For example, in a storage apparatus including a plurality of controller modules (CMs), transmission of data of a memory of one CM to another CM using a direct memory access (DMA) has been conducted.
In addition, a multi-core processor having a plurality of cores may be used as a central processing unit (CPU) included in the CM.
FIG. 11 is a view for describing conventional data transmission using a DMA in a storage apparatus including a controller module (CM) mounted with a multi-core processor.
The storage apparatus 500 illustrated in FIG. 11 includes two CMs 501-1 and 501-2. These CMs 501-1 and 501-2 have the same configuration. Hereinafter, reference numerals 501-1 and 501-2 are used as a reference numeral of the CM when one of a plurality of CMs needs to be specified, but reference numeral 501 is used as a reference numeral of the CM when any CM is designated.
Each CM 501 includes a CPU 502, a memory 503, a switch 504, and a DMA controller 505.
The CPU 502 is a multi-core processor having a plurality of cores 5011, and the memory 503 is connected to the CPU 502. In the storage apparatus 500 illustrated in FIG. 11, each CM 501 has four cores 5011. Hereinafter, these cores 5011 may be represented using signs #0 to #3.
The switch 504 is connected to the CPU 502, and a switch 504 of the other CM 501 is connected to the switch 504. That is, the CM 501-1 and the CM 501-2 are communicably connected to each other through the switches 504 and 504. These switches 504 are connected to each other through, for example, a communication channel according to a standard of peripheral component interconnect express (PCIe).
In addition, in each CM 501, the DMA controller 505 is connected to the switch 504. The DMA controller 505 transmits data between, for example, the memory 503 of the CM 501-1 and the memory 503 of the CM 501-2.
In the CPU 502 which is the multi-core processor, one DMA controller 504 is provided for a plurality of CPU cores 5011.
In addition, a CPU 502 of a transmission source CM501 performs confirmation of consistency of storage data. The consistency confirmation is performed for each data block, such that a check code used for consistency confirmation is added to each data block.
[Patent Literature 1] Japanese Laid-open Patent Publication No. 2016-181126
[Patent Literature 2] Japanese Laid-open Patent Publication No. 2008-197804
In the storage apparatus 500, the data block with the check code for the consistency confirmation has a data size of 520 B (bytes) in which a check code of 8 B is added to a user data of 512 B. Hereinafter, the data block with the check code for the consistency confirmation may be referred to as a data block with a check code. Hereinafter, a unit “Byte” of a data size may be simply represented as “B”.
On the other hand, a max payload size (MPS) of the PCIe used for communication between the CMs 501 is 256 B, and a data size having the highest transmission efficiency in the PCIe is an integral multiple of 256 B.
As described above, unit sizes of data handled in the data block with the check code and the standard of the PCIe do not coincide with each other.
For example, efficient data transmission performed in the data block with the check code, that is, data transmission in units of 520 B is inefficient in the PCIe, and maximum bus performance is unable to be exhibited.
In a data block which has a data size of 520 B and of which the consistency is confirmed, data is transmitted three times at each data size of 256 B-256 B-8 B between the CMs 501. Therefore, particularly at the time of transmitting data corresponding to the data size of the last 8 B, bus use efficiency of the PCIe is deteriorated.